Multiple-Valued PLA Minimization by Concurrent Multiple and Mixed Simulated Annealing
نویسندگان
چکیده
We analyze simulated annealing applied to multiple-valued programmable logic array (MVL PLA) design. Of spec@c interest is the use of parallel processors. We consider the use of loosely-coupled, coarsegrainedparallel systems, and study the relationship between the quality of the solution and computation time, on the one hand, and simulated annealing parameters, start temperature, cooling rate, etc., on the other. We also investigate simulated annealing where there is a mixture of move types. The mixed move approach provides improvement in both the number of product terms and computation time.
منابع مشابه
Multiple-Valued Programmable Logic Array Minmization by Simulated Annealing
We propose a solution to the minimization problem of multiple-valued programmable logic arrays (PLA) that uses simulated annealing. The algorithm accepts a sum-ofproducts expression, divides and recombines the product terms. gradually progressing toward a minimal solution. The input expression can be user-specijied or one produced by another heuristic. Unlike recently studied minimization techn...
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